HPC Connectivity

DSP-Based 112G SerDes, Margin, you can ship.

Positioning
Our DSP-based multi-standard PAM4 SerDes platform delivers 112G lanes engineered for throughput, margin, and system-level practicality across advanced packages, dense boards, and high-speed interconnect paths.
Enabling AI connectivity on advanced process nodes.
Patent-pending design techniques and low-power DSP
Industry-leading tuning for robustness and power optimization
multi-standard PAM4 SerDes platform
delivers 112G-class PAM4 connectivity
engineering

Channel-Resilient SerDes Architecture

The platform is built around reach-aware optimizations, combining adaptive equalization and link training to handle the variability that shows up in real channels. we offer predictable bring-up, stable links, and performance that holds across operating conditions.

capabilities
High-Performance SerDes,
Multiple Applications
Supports multiple chiplet designs
A SerDes foundation that scales with lane counts and advanced packaging connectivity.
Package-integrated optics
Clean, optimized interfaces engineered for efficient short-reach connectivity.
High-speed networking
Built to align with IEEE 802.3 Ethernet needs and modern high-speed link requirements.
Cloud infrastructure
Reach-aware tuning with adaptive DSP for high-throughput links.
integration and validation

Accelerated Bring-up

Includes integrated PRBS and BER capabilities to accelerate link validation and consistent performance across challenging channels.
Supports figure-of-merit tracking for real-time visibility into link margin and faster performance tuning.
Provides comprehensive loopback modes to simplify bring-up, characterization, and system-level debug.
JTAG-based debug enables fast, efficient PHY diagnostics—so you can validate and ship with confidence.

Download the detailed technical specifications and architecture overview.

Download Datasheet Brief
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